As known to the skilled person in the art, applications using electronic circuits integrated on a semiconductor substrate and being able to transmit data at high frequencies are widespread. Electronic circuits integrated on semiconductor, also called chips, are assembled in a package, which comprises a casing of thermosetting resin and incorporates a support frame with electric connection pins. The electronic circuit itself is tied to this frame.
The assembling technology has undergone, in recent times, a development that allows realization of multi-chip systems by overlapping more chips in a same package to form a pile, also called stack. In multi chip systems, there has been the frequent integration of nonvolatile memories, in particular, of the Flash type, with volatile memories, mainly of the DRAM and PSRAM type. These systems are particularly used in cell devices and in wireless applications.
There is need to make the Flash memories compatible with transmission frequencies of volatile memories data. As known to the skilled person in the art, the increase of data transmission frequencies implies an increase in the “noise” on the supplies in the electronic circuit involved in the transmission. The “noise” is linked to a variation of the reference voltages during the transmission of data in the circuit, as well as, to a variation of the output current. This “noise” particularly implies a reduction and a deterioration of the performances of the electronic circuit with an increase of time necessary for the data transmission.
FIG. 1 schematically illustrates an output stage 1′ realized according to the prior art. The output stage 1′ is inserted between a supply terminal 2′ receiving a first reference voltage Vdd′ or supply voltage, and a reference terminal 3′ maintained at a second reference voltage Gnd or ground. The output stage 1′ also has a first input terminal DATA′ and an output terminal PAD′ connected to an external load (not shown). In particular, the output stage 1′ comprises a pre-buffer 10′ connected to the input terminal DATA′ connected in turn to a final buffer 20′ in correspondence with a first 7′ and a second output terminal 8′ of the pre-buffer 10′.
The pre-buffer 10′ comprises a first inverter I1s, which receives a signal from the input terminal DATA′ and is connected, in correspondence with a single terminal 5′, to a second inverter I2s and to a third inverter I3 respectively connected to the first 7′ and to the second output terminal 8′. In this way, at the first output terminal 7′, there is a first signal GATE_PS, which substantially corresponds to a second signal GATE_NS present at the second output terminal 8′.
The output buffer 20′ comprises a first complementary pair of transistors, M1s and M2s, connected to each other to form a first output terminal 13′, connected in turn to the output terminal PAD′. In particular, the transistor M1s is a p-MOS transistor and is connected with the source terminal s1′ to the supply terminal 21 and with a gate terminal g1′ to the first output terminal 7′ of the pre-buffer 10′. Instead, the transistor M2s is connected with a source terminal s2′ to the reference terminal 3′ and with a gate terminal g2′ to the second output terminal 8′ of the pre-buffer 10′.
The output buffer 20′ further comprises a second complementary pair of transistors M3s and M4s, substantially corresponding and connected in parallel to the first complementary pair of transistors M1s and M2s. In particular, the second complementary pair of transistors M3s and M4s is inserted with source terminals s3′ and s4′ respectively connected to the supply terminal 2′ and to the reference terminal 3′. Gate terminals g3′ and g4′ are connected to the first and to the second output terminal 7′ and 8′ of the pre-buffer 10′, and the drain terminals d3′ and d4′ are connected to each other and connected to the first output terminal 13′ to form the output terminal PAD′ of the output stage 1′
In this way, the pre-buffer 10′ drives separately by way of the first signal GATE_Ps and the second signal GATE_Ns the transistors p and n, M1s, M3s and M2s, M4s, respectively, of the output buffer 20′, so as to reduce any possible cross conduction current between the same transistors p and n during the switch of a signal present in the output terminal PAD′ due to a switch of the signal in the input terminal DATA′.
As it is known to the skilled person in the art, the output stages are realized in a substantially symmetrical way and comprise a first section for the driving of an output or final transistor p. For example, in FIG. 1, the transistor M1s and M3s and a second section for the driving of an output or final transistor n, and the transistor M2s and M4s. Such sections operate in a substantially alternated way on the basis of the switch of the signal in the input terminal DATA′ from high to low or vice versa from low to high.
FIG. 2 schematically illustrates a second prior art embodiment of an output stage, globally indicated with 1″. Elements structurally and functionally corresponding to the output stage 1′ previously described and shown in FIG. 1 may be given the same reference numbers by way of illustration. Also in this embodiment, the output stage 1″ comprises a pre-buffer 10′ connected to an input terminal DATA′ and connected, in correspondence with a first 7′ and a second output terminal 8′, to a final buffer 20′.
The output stage 1″ is substantially symmetrical with respect to an intermediate line A-A′ then, by way of clarity and simplicity, the description of a part of the output stage 1″, in particular, the one above the line A-A′ may follow the description of the remaining part of the stage 1″ being logically deducible. The pre-buffer 10′ comprises an inverter I1′ connected to the input terminal DATA′ and connected in turn to a second inverter I2′ in correspondence with an output terminal 5′.
The second inverter I2′ comprises a complementary pair of MOS transistors, in particular, a first p-MOS transistor M1′ and a second n-MOS transistor M2′, inserted with respective source terminals between the supply terminal 2′ and the reference terminal 3′ Respective drain terminals are connected to each other to form the output terminal 7′, and the respective gate terminals are connected to the output terminal 5′ of the first inverter I1′. Moreover, the second transistor M2′ is connected to the reference terminal 3′ by way of the interposition of a third transistor M3′ of the n-MOS type, connected thereto in series, which has a gate terminal driven by a first enable signal EN_P′.
In particular, as shown in FIG. 3, the first enable signal EN_P′ is supplied by a logic circuit 31′ outside the pre-buffer 10′. The logic circuit 31′ comprises a first inverter I9′ and a second inverter I10′ connected in series. The first inverter I9′ receives a general enable signal EN′ of the electronic circuit and supplies the output terminal with a second complementary enable signal EN_N′. The second inverter I10′, which receives the second complementary enable signal EN_N′ at its input terminal, supplies the respective output terminal with the first enable signal EN_P′ which substantially corresponds to the general enable signal EN′ delayed by the inverters I9′ and I10′.
The second inverter I2′ of the pre-buffer 10′ is enabled by the first enable signal EN_P′ and supplies a first signal Gate_P′ at the output terminal 7′ suitable for driving the output buffer 20′. The output buffer 20′ comprises a first final transistor Pfin′ of the pMOS type, which shows a gate terminal gp′ connected to the output terminal 7′ of the pre-buffer 10′, a source terminal connected to the supply terminal 2′, and a drain terminal connected to the output terminal PAD′ of the output stage 1″.
Symmetrically, the pre-buffer 10′ comprises a third inverter I3′ interposed between the reference terminal 3′ and the supply terminal 2′, being enabled by the second enable signal EN_N′ supplied by the logic circuit 31′. This supplies a second signal Gate_N′ at a second output terminal S′ suitable for driving a second final transistor Nfin′, of the n_MOS type, inserted between the output terminal PAD′ of the output buffer 20′ and the reference terminal 3′. In particular, the first signal Gate_P′ and the second signal Gate_N′ are substantially corresponding and alternatively drive the first final transistor Pfin′ and the second final transistor Nin′ of the output buffer 20′.
As known to the skilled person in the art, an electronic circuit as well as the corresponding output stage are connected to the external components through the package interconnections. Therefore, the electric signals present on the interconnection pins connected to reference voltages, in particular, to the first reference voltage present at the supply terminal and to the second reference voltage present at the reference terminal, are not ideal but suffer from the parasite effect of the interconnection lines and of the package.
FIG. 4 schematically shows a pattern with concentrated parameters of an output stage, similar to the one represented in FIGS. 1-3, with connections to the reference voltages, in particular, to the first reference voltage Vdd′ in correspondence with the supply terminal 2′ and to the second reference voltage Gnd′ in correspondence with the reference terminal 3′. The output stage, always indicated with 1′, is connected between an input terminal DATA′ and an output terminal PAD′.
In particular, the pattern shown comprises a first resistance Rvdd′ and a first inductance Lvdd′, both parasitic and proper of the interconnection line to the supply terminal 2′, as well as a second resistance Rgnd′ and a second inductance Lgnd′, both parasitic and proper of the interconnection line to the reference terminal 3′.
Moreover, the real interaction between the output stage 1′ and a semiconductor substrate where the circuit is realized is shown by way of a parasite network RLC′. The network RLC′ comprises a third resistance Rsub′ in series to a third inductance Lsub′ interposed between the output terminal PAD′ and the load LOAD′, as well as a first capacitor Csub′ interposed between the load LOAD′ and the second reference voltage Gnd′. Finally, the pattern of a second capacitor Cload′ or load capacitor is shown connected in parallel to the first capacitor Csub′
During a switch of the logic value present in correspondence with the output terminal PAD′ r there is a breakdown of the first reference voltage Vdd′ or of the second reference voltage Gnd′ according to the transition in progress. In consequence, there is a variation of the driving voltage of the output stage 1′, i.e. of the load voltage Load′. In particular, according to the transition, a current flows from or towards the load capacitor Cload′ and moreover, the first Lvdd′, the second Lgnd′ and the third Lsub′ inductance induce an inductive parasitic contribution, which implies a reduction of the voltage at the output terminal PAD′.
Considering, for example, a switch of the output signal present at the output terminal PAD′ with a rising transition, for example, from a logic value 0 to a logic value 1 according to the scheme of FIG. 2, the first final transistor Pfin′ of the final buffer 20′ may be brought in conduction. However, the parasitic elements and, in particular, the load capacitor Cload′ require a current which inevitably induces, at least on a first transient, an oscillation of the output voltage with a reduction of the first reference voltage Vdd′ at the supply terminal 2′.
This effect reflects on the drain-source voltage difference Vds of the first final transistor Pfin′ of the output buffer 20′, which implies, besides a reduction of the voltage at the output terminal PAD′, also a reduction of the corresponding current value. FIG. 5 reports the known curves characteristic of a MOS transistor. As depicted, it can be observed how the first final transistor Pfin′ of the output buffer 20′ operates, at least during a transient of the output stage 1′, with characteristics comprising an underlying curve and an ideal curve characterized by a gate-source voltage difference Vgs equal to the first reference voltage Vdd′.
In other words, the output stage 1′ realized according to the prior art, under real situations, shows an operation below the ideal condition of the transistors therein due to the parasitic elements always present in a real circuit, which cause undesired variations of the reference voltages with subsequent loss in terms of performances an speed. A possible problem is devising an output stage that is not affected by the oscillations of the reference voltages connected thereto during the high frequency operation by using a simple and functional architecture, so as to overcome the limits or drawbacks still affecting the output stages realized according to the prior art.